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PCA2125
SPI Real-time clock/calendar
Rev. 01 -- 28 July 2008 Product data sheet
1. General description
The PCA2125 is a CMOS real-time clock/calendar optimized for low-power consumption and an operating temperature up to 125 C. Data is transferred via a Serial Peripheral Interface (SPI) bus with a maximum data rate of 6.0 Mbit/s. An alarm and timer function are also available with the possibility to generate a wake-up signal on an interrupt pin. AEC Q100 qualified for automotive applications.
2. Features
I Provides year, month, day, weekday, hours, minutes and seconds based on 32.768 kHz quartz crystal I Resolution: seconds to years I Clock operating voltage: 1.3 V to 5.5 V I Low backup current: typical 0.55 A at VDD = 3.0 V and Tamb = 25 C I 3-line SPI-bus with separate combinable data input and output I Serial interface (at VDD = 1.6 V to 5.5 V) I 1 second or 1 minute interrupt output I Freely programmable timer with interrupt capability I Freely programmable alarm function with interrupt capability I Integrated oscillator capacitor I Internal power-on reset I Open-drain interrupt pin
3. Applications
I Automotive time keeping application I Metering
4. Ordering information
Table 1. Ordering information Package Name PCA2125TS TSSOP14 Description plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT402-1 Type number
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
5. Marking
Table 2. Marking codes Marking code PCA2125 Type number PCA2125TS
6. Block diagram
OSCI OSCILLATOR 32.768 kHz OSCO MONITOR 00h 01h 0Dh POWER-ON RESET TIME 02h VDD VSS 03h 04h 05h 06h 07h WATCHDOG 08h Seconds Minutes Hours Days Weekdays Months Years CONTROL Control_1 Control_2 CLKOUT_control DIVIDER CLOCK OUT CLKOUT
ALARM FUNCTION 09h SDO SDI SCL CE TIMER FUNCTION SPI INTERFACE 0Ah 0Bh 0Ch Minute_alarm Hour_alarm Day_alarm Weekday_alarm INTERRUPT INT
PCA2125
0Eh 0Fh
Timer_control Countdown_timer
001aah664
Fig 1.
Block diagram of PCA2125
PCA2125_1
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PCA2125
SPI Real-time clock/calendar
7. Pinning information
7.1 Pinning
OSCI OSCO n.c. n.c. INT CE VSS
1 2 3 4 5 6 7
001aaf892
14 VDD 13 CLKOUT 12 n.c.
PCA2125
11 n.c. 10 SCL 9 8 SDI SDO
Fig 2.
Pin configuration for TSSOP14
7.2 Pin description
Table 3. Symbol OSCI OSCO n.c. INT CE VSS SDO SDI SCL n.c. CLKOUT VDD Pin description Pin 1 2 3, 4 5 6 7 8 9 10 11, 12 13 14 Description oscillator input oscillator output not connected; do not connect and do not use as feed through; connect to VDD if floating pins are not allowed interrupt output (open-drain; active LOW) chip enable input (active HIGH) with 200 k pull-down resistor ground serial data output, push-pull serial data input; might float when CE inactive serial clock input; might float when CE inactive not connected; do not connect and do not use as feed through; connect to VDD if floating pins are not allowed clock output (open-drain) supply voltage
8. Functional description
The PCA2125 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real-Time Clock (RTC), a programmable clock output, and a 6 MHz SPI-bus. All sixteen registers are designed as addressable 8-bit parallel registers although not all bits are implemented:
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SPI Real-time clock/calendar
* The first two registers at addresses 00h and 01h (Control_1 and Control_2) are used
as control registers.
* Registers at addresses 02h to 08h (Seconds, Minutes, Hours, Days, Weekdays,
Months, Years) are used as counters for the clock function. Seconds, minutes, hours, days, months and years are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock/calendar during a carry condition is prevented.
* Registers at addresses 09h to 0Ch (Minute_alarm, Hour_alarm, Day_alarm,
Weekday_alarm) define the alarm condition.
* Register at address 0Dh (CLKOUT_control) defines the clock out mode. * Registers at addresses 0Eh and 0Fh (Timer_control and Countdown_timer) are used
for the countdown timer function. The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1 ms to more than 4 hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. These are defined in register Control_2 (01h).
8.1 Register overview
The time registers are encoded in BCD to simplify application use. Other registers are either bit-wise or standard binary.
Table 4. Register overview Bits labeled `-' are not implemented and will return a logic 0 when read. Bit positions labeled `0' should always be written with logic 0. Address Register name 7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
[1]
Bit 6 0 SI 5 STOP MSF SECONDS[1] MINUTES[1] YEARS[1] AEN_M AEN_H AEN_D AEN_W TE MINUTE_ALARM[1] AMPM HOUR_ALARM[1] HOUR_ALARM[2] DAY_ALARM[1] COUNTDOWN_TIMER AMPM HOURS[1] HOURS[2] DAYS[1] MONTHS[1] 4 0 TI_TP 3 POR_OVRD AF 2 12_24 TF SECONDS MINUTES HOURS HOURS DAYS WEEKDAYS MONTHS YEARS MINUTE_ALARM HOUR_ALARM HOUR_ALARM DAY_ALARM WEEKDAY_ALARM COF CTD 1 0 AIE 0 0 TIE EXT_TEST MI RF -
Control_1 Control_2 Seconds Minutes Hours Days Weekdays Months Years Minute_alarm Hour_alarm Day_alarm Weekday_alarm CLKOUT_control Timer_control Countdown_timer Ten's place.
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PCA2125
SPI Real-time clock/calendar
[2]
Ten's place in 24 h mode.
8.2 Reset
The PCA2125 includes an internal reset circuit which is active whenever the oscillator is stopped; see Figure 3. The oscillator can be stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to ground.
OSCILLATOR
osc stopped 0 = stopped, 1 = running
reset
SDI
POR OVERRIDE CLEAR Bit POR_OVRD
0 = override inactive 1 = override active
CE
0 = clear override mode 1 = override possible
001aaf898
Fig 3.
Reset system
The oscillator is considered to be stopped during the time between power-up and stable crystal resonance; see Figure 4. This time can be in the range 200 ms to 2 s depending on crystal type, temperature and supply voltage. Whenever an internal reset occurs, the reset flag bit RF is set.
chip in reset
chip not in reset
VDD
oscillation
internal reset t
001aaf897
Fig 4.
Power-on reset
Table 5. Register reset value Bits labeled `-' are not implemented and will return a `0' when read. Bits labeled `X' are undefined at power-up and unchanged by subsequent resets. Address 00h 01h 02h 03h 04h 05h 06h
PCA2125_1
Register name 7 Control_1 Control_2 Seconds Minutes Hours Days Weekdays 0 0 1 6 0 0 X X 5 0 0 X X X X 4 0 X X X X -
Bit 3 1 0 X X X X 2 0 0 X X X X X 1 0 X X X X X 0 0 X X X X X
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PCA2125
SPI Real-time clock/calendar
Table 5. Register reset value ...continued Bits labeled `-' are not implemented and will return a `0' when read. Bits labeled `X' are undefined at power-up and unchanged by subsequent resets. Address 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Register name 7 Months Years Minute_alarm Hour_alarm Day_alarm Weekday_alarm CLKOUT_control Timer_control Countdown_timer X 1 1 1 1 0 X 6 X X X 5 X X X X X 4 X X X X X X Bit 3 X X X X X X 2 X X X X X X 0 X 1 X X X X X X 0 1 X 0 X X X X X X 0 1 X
After reset, the following mode is entered:
* 32.768 kHz on pin CLKOUT active * Power-on reset override available to be set * 24 hour mode is selected
The SPI-bus is initialized whenever the chip enable pin CE is inactive (LOW).
8.2.1 Power-on reset override
The Power-On Reset (POR) duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up the on-board test of the device. The setting of this mode requires that bit POR_OVRD be set to logic 1 and that the signals at the SPI-bus pins SDI and CE are toggled as illustrated in Figure 5. All timings are required minimums. Once the override mode has been entered, the device immediately stops being reset and set-up operation can commence i.e. entry into the external clock test mode via the SPI-bus access. The override mode can be cleared by writing a logic 0 to bit POR_OVRD. Bit POR_OVRD must be set to logic 1 before a re-entry into the override mode is possible. Setting bit POR_OVRD to logic 0 during normal operation has no effect except to prevent accidental entry into the POR override mode. This is the recommended setting.
minimum 500 ns SDI
CE reset override minimum 500 ns minimum 2000 ns
POR override set at this time
001aaf900
Fig 5.
POR override sequence
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SPI Real-time clock/calendar
8.3 Control registers
Table 6. Bit 7 6 5 Control_1 register (address 00h) bit description Symbol EXT_TEST STOP Value Description 0 1 0 0 1 normal mode external clock test mode unused RTC source clock runs RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz, 16.384 kHz or 8.192 kHz is still available) unused power-on reset override facility is disabled; set to logic 0 for normal operation power-on reset override is enabled 24 hour mode is selected 12 hour mode is selected unused Table 11 Section 8.2.1 Section 8.10 Reference Section 8.9
4 3
-
0
POR_OVRD 0 1
2 1 to 0 Table 7. Bit 7 6 5
12_24 -
0 1 0
Control_2 register (address 01h) bit description Symbol MI SI MSF Value Description 0 1 0 1 0 1 minute interrupt is disabled minute interrupt is enabled second interrupt is disabled second interrupt is enabled no minute or second interrupt generated flag set when minute or second interrupt generated; flag must be cleared to clear interrupt interrupt pin follows timer flags interrupt pin generates a pulse no alarm interrupt generated flag set when alarm triggered; flag must be cleared to clear interrupt no countdown timer interrupt generated flag set when countdown timer interrupt generated; flag must be cleared to clear interrupt no interrupt generated from the alarm flag interrupt generated when alarm flag set no interrupt generated from the countdown timer flag interrupt generated when countdown timer flag set Section 8.7 Section 8.7.3 Section 8.5.1 Section 8.7.2 Section 8.6 Reference Section 8.6.1
4 3
TI_TP AF
0 1 0 1
2
TF
0 1
1 0
AIE TIE
0 1 0 1
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SPI Real-time clock/calendar
8.4 Time and date function
The majority of the registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for register Minutes in Table 8.
Table 8. BCD example Double-digit Bit 7 23 00 01 02 : 09 10 : 58 59 Table 9. Bit 7 0 0 0 : 0 0 : 0 0 Bit 6 22 0 0 0 : 0 0 : 1 1 Bit 5 21 0 0 0 : 0 0 : 0 0 Bit 4 20 0 0 0 : 0 1 : 1 1 Digit Bit 3 23 0 0 0 : 1 0 : 1 1 Bit 2 22 0 0 0 : 0 0 : 0 0 Bit 1 21 0 0 1 : 0 0 : 0 0 Bit 0 20 0 1 0 : 1 0 : 0 1
Minutes value (decimal)
Register Seconds (address 02h) bit description Symbol RF Value 0 1 Description clock integrity is guaranteed clock integrity is not guaranteed; chip reset has occurred since flag was last cleared this register holds the current seconds value coded in BCD format
6 to 0
SECONDS[6:0]
00 to 59
Table 10. Bit 7 6 to 0 -
Register Minutes (address 03h) bit description Symbol MINUTES[6:0] Value 0 00 to 59 Description unused this register holds the current minutes value coded in BCD format
Table 11. Bit 6 and 7 12 hour 5 4 to 0 -
Register Hours (address 04h) bit description Symbol Value 0 0 1 HOURS[4:0] 01 to 12 Description unused indicates AM indicates PM this register holds the current hours value coded in BCD format for 12 hour mode this register holds the current hours value coded in BCD format for 24 hour mode
mode[1] AMPM
24 hour mode[1] 5 to 0
[1]
PCA2125_1
HOURS[5:0]
00 to 23
Hour mode is set by bit 12_24 in register Control_1.
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SPI Real-time clock/calendar
Register Days (address 05h) bit description Symbol DAYS[5:0] Value 0 01 to 31 Description unused this register holds the current day value coded in BCD format[1]
Table 12. Bit 6, 7 5 to 0
[1]
The RTC compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00.
Table 13. Bit 3 to 7 2 to 0 -
Register Weekdays (address 06h) bit description Symbol WEEKDAYS[2:0] Value 0 0 to 6 Description unused this register holds the current weekday value; see Table 14
Table 14. Day[1]
Weekday assignments Double-digit Bit 7 Bit 6 X X X X X X X Bit 5 X X X X X X X Bit 4 X X X X X X X Bit 3 X X X X X X X Bit 2 0 0 0 0 1 1 1 X X X X X X X Digit Bit 1 0 0 1 1 0 0 1 Bit 0 0 1 0 1 0 1 0
Sunday Monday Tuesday Wednesday Thursday Friday Saturday
[1]
The weekday assignments can be re-defined by the user.
Table 15. Bit 5 to 7 4 to 0 -
Register Months (address 07h) bit description Symbol MONTHS[4:0] Value 0 01 to 12 Description unused this register holds the current month value coded in BCD format; see Table 16
Table 16. Month
Month assignments Double-digit Bit 7 Bit 6 X X X X X X X X X Bit 5 X X X X X X X X X Bit 4 0 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 1 1 Bit 2 0 0 0 1 1 1 1 0 0 X X X X X X X X X Digit Bit 1 0 1 1 0 0 1 1 0 0 Bit 0 1 0 1 0 1 0 1 0 1
January February March April May June July August September
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Month assignments ...continued Double-digit Bit 7 Bit 6 X X X Bit 5 X X X Bit 4 1 1 1 Bit 3 0 0 0 Bit 2 0 0 0 X X X Digit Bit 1 0 0 1 Bit 0 0 1 0
Table 16. Month October November December Table 17. Bit 7 to 0
Register Years (address 08h) bit description Symbol YEARS[7:0] Value 00 to 99 Description this register holds the current year value coded in BCD format
Figure 6 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
12_24 hour mode
HOURS
LEAP YEAR CALCULATION
DAYS
WEEKDAY
MONTHS
YEARS
001aaf901
Fig 6.
Data flow for the time function
8.5 Alarm function
When one or several alarm registers are loaded with a valid minute, hour, day or weekday value and its corresponding alarm enable not bit (AENx) is logic 0, then that information is compared with the current minute, hour, day and weekday value.
Table 18. Bit 7 6 to 0 Register Minute_alarm (address 09h) bit description Symbol AEN_M MINUTE_ALARM[6:0] Value 0 1 00 to 59 Description minute alarm is enabled minute alarm is disabled this register holds the minute alarm value coded in BCD format
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Register Hour_alarm (address 0Ah) bit description Symbol AEN_H AMPM HOUR_ALARM Value 0 1 0 0 1 01 to 12 Description hour alarm is enabled hour alarm is disabled unused indicates AM indicates PM this register holds the hour alarm value coded in BCD format when in 12 hour mode this register holds the hour alarm value coded in BCD format when in 24 hour mode
Table 19. Bit 7 6 5 4 to 0
12 hour mode
24 hour mode 5 to 0 HOUR_ALARM 00 to 23
Table 20. Bit 7 6 5 to 0
Register Day_alarm (address 0Bh) bit description Symbol AEN_D DAY_ALARM Value 0 1 0 01 to 31 Description day alarm is enabled day alarm is disabled unused this register holds the day alarm value coded in BCD format
Table 21. Bit 7 3 to 6 2 to 0
Register Weekday_alarm (address 0Ch) bit description Symbol AEN_W Value 0 1 0 WEEKDAY_ALARM 0 to 6 Description weekday alarm is enabled weekday alarm is disabled unused this register holds the weekday alarm value
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check now signal MINUTE AEN MINUTE ALARM = MINUTE TIME
example MINUTE AEN = 1 1 0 HOUR AEN
HOUR ALARM = HOUR TIME set alarm flag, AF DAY AEN DAY ALARM = DAY TIME
WEEKDAY AEN WEEKDAY ALARM = WEEKDAY TIME
001aaf902
Fig 7.
Alarm function block diagram
Generation of interrupts from the alarm function is described in Section 8.7.3.
8.5.1 Alarm flag
When all enabled comparisons first match, the alarm flag bit AF is set. Bit AF will remain set until cleared by software. Once bit AF has been cleared it will only be set again when the time increments once more to match the alarm condition. Alarm registers which have their bit AENx at logic 1 are ignored. Figure 8 shows an example for clearing bit AF, but leaving bit MSF and bit TF unaffected. The flags are cleared by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior.
minutes counter
44
45
46
minute alarm
45
AF
INT when AIE = 1
001aaf903
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 8.
Alarm flag timing
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SPI Real-time clock/calendar
To prevent the timer flags being overwritten while clearing bit AF, a logic AND is performed during a write access. The flag is reset by writing a logic 0 but its value is not affected by writing a logic 1.
Table 22. Register Control_2 Flag location in register Control_2 Bit 7 Bit 6 Bit 5 MSF Bit 4 Bit 3 AF Bit 2 TF Bit 1 Bit 0 -
Table 23 shows what instruction must be sent to clear bit AF. In this example, bit MSF and bit TF are unaffected.
Table 23. Register Control_2 Example to clear only AF (bit 3) in register Control_2 Bit 7 Bit 6 Bit 5 1 Bit 4 Bit 3 0 Bit 2 1 Bit 1 Bit 0 -
8.6 Timer functions
The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1 ms to more than 4 hours. There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. Registers Control_2 (01h), Timer_control (0Eh) and Countdown_timer (0Fh) are used to control the timer function and output.
Table 24. Bit 7 6 to 2 1 to 0 Register Timer_control (address 0Eh) bit description Symbol TE CTD[1:0] Value 0 1 0 00 01 10 11 Table 25. Bit 7 to 0 Description countdown timer is disabled countdown timer is enabled unused 4096 Hz countdown timer source clock 64 Hz countdown timer source clock 1 Hz countdown timer source clock
1 Hz 60
Reference Section 8.6.2
countdown timer source clock
Register Countdown_timer (address 0Fh) bit description Value 00h to FFh Description countdown value = n. n CountdownPeriod = -------------------------------------------------------------SourceClockFrequency Reference Section 8.6.2
Symbol COUNTDOWN_TIMER[7:0]
8.6.1 Second and minute interrupt
The second and minute interrupts (bits SI and MI) are pre-defined timers for generating periodic interrupts. The timers can be enabled independently of one another, however a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see Figure 9.
PCA2125_1
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SPI Real-time clock/calendar
seconds counter
58
59
59
00
00
01
minutes counter
11
12
INT
MSF
001aai520
a. INT and MSF when SI enabled (MSF flag not cleared after an interrupt)
seconds counter
58
59
59
00
00
01
minutes counter
11
12
INT
MSF
001aai521
b. INT and MSF when only MI enabled
Bit TI_TP is set to logic 1 resulting in 164 Hz wide interrupt pulse.
Fig 9. Table 26. 0 1 0 1
INT example for bits SI and MI Effect of bits MI and SI on INT generation Second interrupt (bit SI) Result 0 0 1 1 no interrupt generated an interrupt once per minute an interrupt once per second an interrupt once per second
Minute interrupt (bit MI)
The minute and second flag (bit MSF) is set to logic 1 when either the seconds or the minutes counter increments according to the currently enabled interrupt. The flag can be read and cleared by the interface. The status of bit MSF does not affect the INT pulse generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT pulse will still be generated. The purpose of the flag is to allow the controlling system to interrogate the PCA2125 and identify the source of the interrupt such as the minute/second or countdown timer.
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Effect of bits MI and SI on bit MSF Second interrupt (bit SI) Result 0 0 1 1 MSF never set MSF set when minutes counter increments[1] MSF set when seconds counter increments MSF set when seconds counter increments
Table 27. 0 1 0 1
[1]
Minute interrupt (bit MI)
In the case of bit MI = 1 and bit SI = 0, bit MSF will be cleared automatically after 1 second.
8.6.2 Countdown timer function
The 8-bit countdown timer at address 0Fh is controlled by the timer control register at address 0Eh. The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 160 Hz), and enables or disables the timer.
Table 28. Bits CTD1 and CTD0 for timer frequency selection and countdown timer durations Timer source clock frequency 4096 Hz 64 Hz 1 Hz
1 60
Bits CTD[1:0]
Delay Minimum timer duration Maximum timer duration n=1 n = 255 244 s 15.625 ms 1s 60 s[1]
1 60
00 01 10 11
[1]
62.256 ms 3.984 s 255 s 4 h 15 min
Hz
When not in use, bits CTD[1:0] must be set to
Hz for power saving.
Remark: Note that all timings which are generated from the 32.768 kHz oscillator are based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency will result in a corresponding deviation in timings. This is not applicable to interface timing. The timer counts down from a software-loaded 8-bit binary value n. Loading the counter with 0 effectively stops the timer. Values from 1 to 255 are valid. When the counter reaches 1, the countdown timer flag (bit TF) will be set and the counter automatically re-loads and starts the next timer period. Reading the timer will return the current value of the countdown counter; see Figure 10.
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countdown value, n
xx
03
timer source clock
countdown counter
xx
03
02
01
03
02
01
03
02
01
03
TE
TF
INT n duration of first timer period after enable may range from n - 1 to n + 1 n
001aaf906
In the example it is assumed that the timer flag is cleared before the next countdown period expires and that the INT is set to pulsed mode.
Fig 10. General countdown timer behavior
If a new value of n is written before the end of the current timer period, then this value will take immediate effect. NXP Semiconductors does not recommend changing n without first disabling the counter (by setting bit TE = 0). The update of n is asynchronous with the timer clock, therefore changing it without setting bit TE = 0 will result in a corrupted value loaded into the countdown counter which results in an undetermined countdown period for the first period. The countdown value n will however be correctly stored and correctly loaded on subsequent timer periods. When the countdown timer flag is set, an interrupt signal on INT will be generated provided that this mode is enabled. See Section 8.7.2 for details on how the interrupt can be controlled. When starting the timer for the first time, the first period will have an uncertainty which is a result of the enable instruction being generated from the interface clock which is asynchronous with the timer source clock. Subsequent timer periods will have no such delay. The amount of delay for the first timer period will depend on the chosen source clock; see Table 29.
Table 29. 4096 Hz 64 Hz 1 Hz
1 60
First period delay for timer counter value n Minimum timer period n n (n - 1) +
1 64
Timer source clock
Maximum timer period n+1 n+1
Hz
n + 164 Hz n + 164 Hz
Hz
(n - 1) + 164 Hz
At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF can only be cleared by software. The asserted bit TF can be used to generate an interrupt (INT). The interrupt can be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is used to control this mode selection and the interrupt output can be disabled with bit TIE.
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When reading the timer, the current countdown value is returned and not the initial value n. For accurate read back of the countdown value, the SPI-bus clock (SCL) must be operating at a frequency of at least twice the selected timer clock. Since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results.
8.6.3 Timer flags
When a minute or second interrupt occurs, bit MSF is set to logic 1. Similarly, at the end of a timer countdown, bit TF is set to logic 1. These bits maintain their value until overwritten by software. If both countdown timer and minute/second interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access. The flag is reset by writing a logic 0 but its value is not affected by writing a logic 1. Three examples are given for clearing the flags. Flags MSF and TF are cleared by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior.
Table 30. Register Control_2 Flag location in register Control_2 Bit 7 Bit 6 Bit 5 MSF Bit 4 Bit 3 AF Bit 2 TF Bit 1 Bit 0 -
Table 31, Table 32 and Table 33 show what instruction must be sent to clear the appropriate flag.
Table 31. Register Control_2 Table 32. Register Control_2 Table 33. Register Control_2 Example to clear only TF (bit 2) in register Control_2 Bit 7 Bit 6 Bit 5 1 Bit 4 Bit 3 1 Bit 2 0 Bit 1 Bit 0 -
Example to clear only MSF (bit 5) in register Control_2 Bit 7 Bit 6 Bit 5 0 Bit 4 Bit 3 1 Bit 2 1 Bit 1 Bit 0 -
Example to clear both TF and MSF (bits 2 and 5) in register Control_2 Bit 7 Bit 6 Bit 5 0 Bit 4 Bit 3 1 Bit 2 0 Bit 1 Bit 0 -
Clearing the alarm flag (bit AF) operates in exactly the same way; see Section 8.5.1.
8.7 Interrupt output
An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits of control register 2. Interrupts can be sourced from three places: second/minute timer, countdown timer and alarm function. Bit TI_TP configures the timer generated interrupts to be either a pulse or to follow the status of the interrupt flags (bits TF and MSF).
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PCA2125
SPI Real-time clock/calendar
SI MSF: MINUTE SECOND FLAG SET CLEAR MI to interface: read MSF 0 PULSE GENERATOR 1 TRIGGER CLEAR from interface: clear MSF TE TF: TIMER SET CLEAR PULSE GENERATOR 2 TRIGGER CLEAR from interface: clear TF AF: ALARM FLAG SET CLEAR from interface: clear AF to interface: read AF AIE to interface: read TF 0 1 TI_TP INT 1 SI MI
SECONDS COUNTER
MINUTES COUNTER
TIE
COUNTDOWN COUNTER
set alarm flag, AF
001aaf907
When bits SI, MI, TIE and AIE are all disabled, pin INT will remain high-impedance.
Fig 11. Interrupt scheme
Remark: Note that the interrupts from the three groups are wired-OR, meaning they will mask one another; see Figure 11.
8.7.1 Minute and second interrupts
The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and consequently generates a pulse of 164 second duration. If the MSF flag is clear before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure 12. Instructions for clearing MSF are given in Section 8.6.3.
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seconds counter
58
59
MSF
INT
(1)
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf908
(1) Indicates normal duration of INT pulse (bit TI_TP = 1).
Fig 12. Example of shortening the INT pulse by clearing the MSF flag
The timing shown for clearing bit MSF in Figure 12 is also valid for the non-pulsed interrupt mode i.e. when bit TI_TP = 0, where the pulse can be shortened by setting both bits MI and SI to logic 0.
8.7.2 Countdown timer interrupts
Generation of interrupts from the countdown timer is controlled via bit TIE; see Table 7. The pulse generator for the countdown timer interrupt also uses an internal clock which is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies; see Table 34.
Table 34. INT operation (bit TI_TP = 1) INT period (s) n = 1[1] 4096 64 1
1 60 1 8192 1 128 1 64 1 64
Source clock (Hz)
n>1
1 1 1 1 4096 64 64 64
[1]
n = loaded countdown value. Timer stopped when n = 0.
If the TF flag is clear before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure 13. Instructions for clearing TF are given in Section 8.6.3.
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countdown counter
01
n
TF
INT
(1)
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf909
(1) Indicates normal duration of INT pulse (bit TI_TP = 1).
Fig 13. Example of shortening the INT pulse by clearing the TF flag
The timing shown for clearing bit TF in Figure 13 is also valid for the non-pulsed interrupt mode i.e. when bit TI_TP = 0, where the pulse can be shortened by setting bit TIE = 0.
8.7.3 Alarm interrupts
Generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the INT pin follows the status of bit AF. Clearing bit AF will immediately clear INT. No pulse generation is possible for alarm interrupts; see Figure 14.
minute counter
44
45
minute alarm
45
AF
INT
SCL 8th clock instruction CLEAR INSTRUCTION
001aaf910
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 14. AF timing
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8.8 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by control bits COF[2:0] in register CLKOUT_control (0Dh). Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Pin CLKOUT is an open-drain output and enabled at power-on. When disabled the output is LOW. The duty cycle of the selected clock is not controlled, but due to the nature of the clock generation, all clock frequencies, except 32.768 kHz, have a duty cycle of 50 : 50. The `stop' function can also affect the CLKOUT signal, depending on the selected frequency. When `stop' is active, the CLKOUT pin will generate a continuous LOW for those frequencies that can be stopped. For more details, see Section 8.10.
Table 35. 000 001 010 011 100 101 110 111
[1]
CLKOUT frequency selection CLKOUT frequency (Hz) 32768 16384 8192 4096 2048 1024 1 CLKOUT = LOW Typical duty cycle[1] (%) 60 : 40 to 40 : 60 50 : 50 50 : 50 50 : 50 50 : 50 50 : 50 50 : 50 Effect of `stop' no effect no effect no effect CLKOUT = LOW CLKOUT = LOW CLKOUT = LOW CLKOUT = LOW
Bits COF[2:0]
Duty cycle definition: HIGH-level time (%) : LOW-level time (%).
8.9 External clock test mode
A test mode is available which allows for on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST in register Control_1 making pin CLKOUT an input. The test mode replaces the internal signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT generates an increment of one second. The signal applied to pin CLKOUT should have a minimum HIGH width of 300 ns and a minimum period of 1000 ns. The internal clock, now sourced from pin CLKOUT, is divided down to 1 Hz by a 26 divide chain called a prescaler; see Section 8.10. The prescaler can be set into a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. STOP must be cleared before the prescaler can operate again. From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. Operation example:
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1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1). 2. Set STOP (register Control_1, bit STOP = 1). 3. Clear STOP (register Control_1, bit STOP = 0). 4. Set time registers to desired value. 5. Apply 32 clock pulses to pin CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to pin CLKOUT. 8. Read time registers to see the second change. Repeat steps 7 and 8 for additional increments.
8.10 STOP bit function
The STOP bit function allows the accurate starting of the time circuits. The stop function will cause the upper part of the prescaler (F2 to F14) to be held at reset, thus no 1 Hz ticks will be generated. The time circuits can then be set and will not increment until the stop is released; see Figure 15. Stop will not affect the output of 32768 Hz, 16384 Hz or 8192 Hz; see Section 8.8.
OSC STOP DETECTOR 32768 Hz 16384 Hz 8192 Hz
reset
4096 Hz
F0
F1
F2 RES
F13 RES
2 Hz
F14 1 Hz tick RES stop
OSC
512 Hz
CLKOUT source 8192 Hz 16384 Hz
001aaf911
Fig 15. Stop bit functional diagram
The lower two stages of the prescaler (F0 and F1) are not reset and because the SPI-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8192 Hz cycle; see Figure 16.
8192 Hz
stop released 0 s to 122 s
001aaf912
Fig 16. STOP bit release timing
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The first increment of the time circuits is between 0.499888 s and 0.500000 s after stop is released. The uncertainty is caused by prescaler bits F0 and F1 not being reset; see Table 36.
Table 36. Bit STOP Example: first increment of time circuits after stop release Prescaler bits F0F1-F2 to F14 0 1 1 0
[1]
1 Hz tick
Time hh:mm:ss 12:45:12 12:45:12 08:00:00 08:00:00 08:00:00 08:00:00 08:00:00 : 08:00:00 08:00:01 08:00:01 : 08:00:01 08:00:01 08:00:01 : 08:00:01 08:00:02
Comment
Clock is running normally 01-0 0001 1101 0100 XX-0 0000 0000 0000 XX-0 0000 0000 0000 XX-0 0000 0000 0000 XX-1 0000 0000 0000 XX-0 1000 0000 0000 XX-1 1000 0000 0000 : 11-1 1111 1111 1110 00-0 0000 0000 0001 10-0 0000 0000 0001 : 11-1 1111 1111 1111 00-0 0000 0000 0000 10-0 0000 0000 0000 : 11-1 1111 1111 1110 00-0 0000 0000 0001
[1] F0 is clocked at 32.768 kHz.
prescaler counting normally prescaler is reset; time circuits are frozen prescaler is reset; time circuits are frozen prescaler is now running
Stop is activated by user. F0F1 are not reset and values can not be predicted externally New time is set by user Stop is released by user
0 to 1 transition of F14 increments the time circuits
0 to 1 transition of F14 increments the time circuits
0.499888 s to 0.500000 s
1s
001aaf913
Fig 17. Increment of time circuit
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8.11 3-line SPI
Data transfer to and from the device is made via a 3-wire SPI-bus; see Table 37. The data lines for input and output are split. The data input and output lines can be connected together to facilitate a bidirectional data bus. The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first; see Figure 18.
Table 37. Pin CE Serial interface Description when LOW, the interface is reset; pull-down resistor included; active input can be higher than VDD, but must not be wired HIGH permanently when pin CE = LOW, this input might float; input can be higher than VDD when pin CE = LOW, this input might float; input can be higher than VDD; input data is sampled on the rising edge of SCL push-pull output; drives from VSS to VDD; output data is changed on the falling edge of SCL
Function chip enable input
SCL SDI SDO
serial clock input serial data input serial data output
The transmission is controlled by the active HIGH chip enable signal CE. The first byte transmitted is the command byte. Subsequent bytes will be either data to be written or data to be read. Data is captured on the rising edge of the clock and transferred internally on the falling edge.
data bus
COMMAND
DATA
DATA
DATA
chip enable
001aaf914
Fig 18. Data transfer overview
The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the following bytes will be read or write information.
Table 38. Bit 7 Command byte definition Symbol R/W 0 1 6 to 4 3 to 0 SA RA 001 Value Description data read or data write selection write data read data subaddress; other codes will cause the device to ignore data transfer
00h to 0Fh register address range
In Figure 19 the Seconds register is set to 45 seconds and the Minutes register to 10 minutes.
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R/W b7 0 b6 0 b5 0 b4 1 b3 0
addr 02HEX b2 0 b1 1 b0 0 b7 0 b6 1
seconds data 45BCD b5 0 b4 0 b3 0 b2 1 b1 0 b0 1 b7 0 b6 0
minutes data 10BCD b5 0 b4 1 b3 0 b2 0 b1 0 b0 0
SCL
SDI
CE
address counter
xx
02
03
04
001aaf915
Fig 19. Serial bus write example
In Figure 20 the Months and Years registers are read. In this example, pins SDI and SDO are not connected together. In this configuration, it is important that pin SDI is never left floating: it must always be driven either HIGH or LOW. If pin SDI is left open, high IDD currents will result.
R/W b7 1 b6 0 b5 0 b4 1 b3 0
addr 07HEX b2 1 b1 1 b0 1 b7 0 b6 0
months data 11BCD b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 b7 0 b6 0
years data 06BCD b5 0 b4 0 b3 0 b2 1 b1 1 b0 0
SCL
SDI
SDO
CE
address counter
xx
07
08
09
001aaf916
Fig 20. Serial bus read example
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9. Internal circuitry
VDD OSCI
CLKOUT OSCO SCL INT SDI CE SDO VSS
PCA2125
001aaf895
Fig 21. Device diode protection diagram
10. Limiting values
Table 39. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD IDD VI VO II IO Ptot Tamb Tstg Vesd supply voltage supply current input voltage output voltage input current output current total power dissipation ambient temperature storage temperature electrostatic discharge voltage HBM MM CDM Ilu
[1] [2] [3] [4]
[1] [2] [3] [4]
Conditions
Min -0.5 -50 -0.5 -0.5 -10 -10 -40 -65 -
Max +6.5 +50 +6.5 +6.5 +10 +10 300 +125 +150 2000 200 2000 100
Unit V mA V V mA mA mW C C V V V mA
latch-up current
HBM: Human Body Model, according to JESD22-A114. MM: Machine Model, according to JESD22-A115. CDM: Charged-Device Model, according to JESD22-C101. Latch-up testing, according to JESD78.
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11. Static characteristics
Table 40. Static characteristics VDD = 1.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +125 C; fosc = 32.768 kHz; quartz Rs = 60 k; CL = 12.5 pF; unless otherwise specified. Symbol VDD Parameter supply voltage Conditions SPI-bus inactive; for clock data integrity SPI-bus active IDD supply current SPI-bus active fSCL = 6.0 MHz fSCL = 1.0 MHz SPI-bus inactive; CLKOUT disabled; VDD = 2.0 V to 5.0 V Tamb = 25 C Tamb = -40 C to +125 C SPI-bus inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz Tamb = 25 C VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V Tamb = -40 C to +125 C VDD = 5.0 V VDD = 3.0 V VDD = 2.0 V Inputs VI VI VIL VIH IL CI Rpd Outputs VO VO VOH VOL VOL output voltage output voltage HIGH-level output voltage LOW-level output voltage LOW-level output voltage pins OSCO and SDO pins CLKOUT and INT; refers to external pull-up voltage pin SDO pin SDO pins CLKOUT and INT; VDD = 5 V; IOL = 1.5 mA 0.8VDD VSS VSS VDD + 0.5 V 5.5 VDD 0.2VDD 0.4 V V V V input voltage input voltage LOW-level input voltage HIGH-level input voltage leakage current input capacitance pull-down resistance pin CE VI = VDD or VSS; on pins SDI, SCL and OSCI
[3] [2] [1]
Min 1.3 1.6 -
Typ -
Max 5.5 5.5 500 85
Unit V V A A
Supply: pin VDD
-
550 760
1800
nA nA
-0.5 -0.5 VSS 0.7VDD -1 -
1000 760 640 0 240
2250 1950 1900
nA nA nA nA nA nA
pin OSCI pins CE, SDI, SCL
VDD + 0.5 V 5.5 0.3VDD VDD +1 7 550 V V V A pF k
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Table 40. Static characteristics ...continued VDD = 1.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +125 C; fosc = 32.768 kHz; quartz Rs = 60 k; CL = 12.5 pF; unless otherwise specified. Symbol IOH IOL IOL ILO Cext
[1] [2] [3]
Parameter HIGH-level output current LOW-level output current LOW-level output current output leakage current external capacitance
Conditions pin SDO; VOH = 4.6 V; VDD = 5 V pins INT, SDO and CLKOUT; VOL = 0.4 V; VDD = 5 V pin OSCO; VOL = 0.4 V; VDD = 5 V VO = VDD or VSS
Min -1.5 -1 -1 -
Typ 0 25
Max 1.5 +1 -
Unit mA mA mA A pF
For reliable oscillator start at power-up: VDD = VDD(min) + 0.3 V. Timer source clock = 160 Hz; voltage on pins CE, SDI and SCL at VDD or VSS. Implicit by design.
12. Dynamic characteristics
Table 41. Dynamic characteristics VDD = 1.6 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +125 C. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Pin SCL fclk(SCL) tSCL tclk(H) tclk(L) tr tf Pin CE tsu(CE) th(CE) trec(CE) tw(CE) Pin SDI tsu th Pin SDO td(R)SDO tdis(SDO) SDO read delay time bus load = 85 pF SDO disable time no load value to avoid bus conflict
[1]
Parameter
Conditions
VDD = 1.6 V Min Max 1.5 100 100 0.99 320 50 -
VDD = 2.7 V Min 210 100 110 30 60 100 15 60 0 Max 4.76 100 100 0.99 110 30 -
VDD = 4.5 V Min 200 100 100 30 40 100 15 40 0 Max 5.00 100 100 0.99 100 30 -
VDD = 5.5 V Unit Min 160 70 90 30 30 100 10 30 0 Max 6.25 MHz 100 100 ns ns ns ns ns ns ns ns
SCL clock frequency SCL time clock HIGH time clock LOW time rise time fall time CE set-up time CE hold time CE recovery time CE pulse width set-up time hold time
660 320 320 30 100 100 25 100 0
0.99 s 90 25 ns ns ns ns ns
tt(SDI-SDO) transition time from SDI to SDO
[1]
Bus will be held up by bus capacitance; use RC time constant with application values.
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tw(CE) CE tsu(CE) tr tf SCL 20% tclk(L) tclk(H) 80% th(CE) trec(CE)
WRITE
tsu th
SDI
R/W
SA2
RA0
b7
b6
b0
SDO
Hi Z
READ
SDI
b7
b6
b0 tt(SDI-SDO) td(R)SDO tdis(SDO) b6 b0
001aag900
SDO
Hi Z
b7
Fig 22. SPI interface timing
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13. Application information
13.1 Application diagram
1F supercapacitor
OSCI
VDD
CLKOUT
CE SCL
OSCO
PCA2125
VSS
SDI SDO
INT
001aaf918
The 1 farad capacitor is used as a standby and back-up supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC can operate for several weeks.
Fig 23. Application diagram
13.2 Quartz frequency adjustment
1. Method 1: fixed OSCI capacitor A fixed capacitor can be used whose value can be determined by evaluating the average capacitance necessary for the application layout; see Figure 23. The frequency is best measured via the 32.768 kHz signal at pin CLKOUT available after power-on. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 x 10-6). An average deviation of 5 minutes per year can be easily achieved. 2. Method 2: OSCI trimmer Fast setting of a trimmer is possible using the 32.768 kHz signal at pin CLKOUT available after power-on. 3. Method 3: OSCO output Direct measurement of OSCO output (accounting for test probe capacitance).
14. Test information
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for use in automotive applications.
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15. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 24. Package outline SOT402-1 (TSSOP14)
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16. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
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* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 25) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 42 and 43
Table 42. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 43. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 25. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Revision history
Table 44. Revision history Release date 20080728 Data sheet status Product data sheet Change notice Supersedes Document ID PCA2125_1
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19. Legal information 20. Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.1 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
20.2 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
20.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA2125_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 28 July 2008
35 of 36
NXP Semiconductors
PCA2125
SPI Real-time clock/calendar
22. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.3 8.4 8.5 8.5.1 8.6 8.6.1 8.6.2 8.6.3 8.7 8.7.1 8.7.2 8.7.3 8.8 8.9 8.10 8.11 9 10 11 12 13 13.1 13.2 14 14.1 15 16 17 17.1 17.2 17.3 17.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Register overview . . . . . . . . . . . . . . . . . . . . . . . 4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-on reset override . . . . . . . . . . . . . . . . . . 6 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7 Time and date function . . . . . . . . . . . . . . . . . . . 8 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 10 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timer functions . . . . . . . . . . . . . . . . . . . . . . . . 13 Second and minute interrupt. . . . . . . . . . . . . . 13 Countdown timer function . . . . . . . . . . . . . . . . 15 Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 17 Minute and second interrupts . . . . . . . . . . . . . 18 Countdown timer interrupts. . . . . . . . . . . . . . . 19 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 20 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 21 External clock test mode. . . . . . . . . . . . . . . . . 21 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 22 3-line SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 Static characteristics. . . . . . . . . . . . . . . . . . . . 27 Dynamic characteristics . . . . . . . . . . . . . . . . . 28 Application information. . . . . . . . . . . . . . . . . . 30 Application diagram . . . . . . . . . . . . . . . . . . . . 30 Quartz frequency adjustment . . . . . . . . . . . . . 30 Test information . . . . . . . . . . . . . . . . . . . . . . . . 30 Quality information . . . . . . . . . . . . . . . . . . . . . 30 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31 Handling information. . . . . . . . . . . . . . . . . . . . 32 Soldering of SMD packages . . . . . . . . . . . . . . 32 Introduction to soldering . . . . . . . . . . . . . . . . . 32 Wave and reflow soldering . . . . . . . . . . . . . . . 32 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 32 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 33 18 19 20 20.1 20.2 20.3 21 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 35 35 35 35 35 35 36
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 July 2008 Document identifier: PCA2125_1

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